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Filterless High Efficiency Mono 3 W Class-D Audio Amplifier SSM2317
FEATURES
Filterless Class-D amplifier with - modulation Automatic level control (ALC) improves dynamic range and prevents clipping 3 W into 3 load and 1.4 W into 8 load at 5.0 V supply with <10% total harmonic distortion (ALC off) 700 mW into 8 load at 4.2 V supply (ALC 80%) 93% efficiency at 5.0 V, 1.4 W into 8 speaker >93 dB signal-to-noise ratio (SNR) Single-supply operation from 2.5 V to 5.5 V 20 nA ultralow shutdown current Short-circuit and thermal protection Available in 9-ball, 1.5 mm x 1.5 mm WLCSP Pop-and-click suppression Built-in resistors reduce board component count Default fixed 18 dB or user-adjustable gain setting
supply. It is capable of delivering 3 W of continuous output power with <1% THD + N driving a 3 load from a 5.0 V supply. The SSM2317 features a high efficiency, low noise modulation scheme that does not require any external LC output filters. The modulation continues to provide high efficiency even at low output power. It operates with 93% efficiency at 1.4 W into 8 or 85% efficiency at 3 W into 3 from a 5.0 V supply and has an SNR of >93 dB. Spread-spectrum pulse density modulation is used to provide lower EMI radiated emissions compared with other Class-D architectures. Automatic level control (ALC) can be activated to suppress clipping and improve dynamic range. This feature only requires one external resistor tied to GND via the VTH pin and an activation voltage on the ALC_EN pin. The SSM2317 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin. The device also includes pop-and-click suppression circuitry. This minimizes voltage glitches at the output during turn-on and turnoff, reducing audible noise on activation and deactivation. The default gain of the SSM2317 is 18 dB, but users can reduce the gain by using a pair of external resistors (see the Gain section). The SSM2317 is specified over the commercial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 9-ball, 1.5 mm x 1.5 mm wafer level chip scale package (WLCSP).
APPLICATIONS
Mobile phones MP3 players Portable gaming Portable electronics Educational toys
GENERAL DESCRIPTION
The SSM2317 is a fully integrated, high efficiency, Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.5 V
FUNCTIONAL BLOCK DIAGRAM
10F 0.1F 0.1F1 AUDIO IN+ 80k VBATT 2.5V TO 5.5V VDD
IN+
10k
SSM2317
OUT+ MODULATOR (-) 0.1F1 FET DRIVER OUT-
AUDIO IN-
IN-
10k 80k
SHUTDOWN
SD
BIAS
ALC ALC_EN VTH RTH ALC ENABLE
INTERNAL OSCILLATOR
POP-AND-CLICK SUPPRESSION GND
1 INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07242-001
SSM2317 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Typical Application Circuits.......................................................... 13 Theory of Operation ...................................................................... 14 Overview...................................................................................... 14 Gain .............................................................................................. 14 Pop-and-Click Suppression ...................................................... 14 Output Modulation Description .............................................. 14 Layout .......................................................................................... 14 Input Capacitor Selection .......................................................... 15 Proper Power Supply Decoupling ............................................ 15 Automatic Level Control (ALC) ............................................... 15 Operating Modes ........................................................................ 15 Attack Time, Hold Time, and Release Time ........................... 15 Output Threshold ....................................................................... 16 Enable/Disabling ALC ............................................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
6/08--Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 2 ............................................................................ 5 Changes to Figure 17 and Figure 18 ............................................... 9 Changes to Figure 39 and Figure 40 ............................................. 13 Changes to Ordering Guide .......................................................... 17 3/08--Revision 0: Initial Version
Rev. A | Page 2 of 20
SSM2317 SPECIFICATIONS
VDD = 5.0 V, TA = 25C, RL = 8 + 33 H, ALC = off, unless otherwise noted. Table 1.
Parameter DEVICE CHARACTERISTICS Output Power Symbol PO Conditions RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 3 , THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 3 , THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V PO = 1.4 W, 8 , VDD = 5.0 V PO = 1 W into 8 , f = 1 kHz, VDD = 5.0 V PO = 0.5 W into 8 , f = 1 kHz, VDD = 3.6 V 1.0 VCM = 2.5 V 100 mV at 217 Hz, output referred Gain = 18 dB Guaranteed from PSRR test VDD = 2.5 V to 5.0 V, dc input floating VRIPPLE = 100 mV at 217 Hz, inputs ac grounded, CIN = 0.1 F VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V VIN = 0 V, load = 8 + 33 H, VDD = 5.0 V VIN = 0 V, load = 8 + 33 H, VDD = 3.6 V VIN = 0 V, load = 8 + 33 H, VDD = 2.5 V SD = GND 2.5 70 57 280 2.0 5.5 85 60 3.6 3.2 2.7 3.7 3.3 2.8 20 18 10 10 1.2 0.5 28 5 >100 Min Typ 1.42 0.72 1.77 0.91 2.53 1.27 3.16 1 1.59 3.111 1.55 3.891 1.94 93 0.02 0.02 VDD - 1.0 Max Unit W W W W W W W W W W W W % % % V dB kHz mV V dB dB mA mA mA mA mA mA nA dB k k V V ms s k
Efficiency Total Harmonic Distortion + Noise Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio
THD + N VCM CMRRGSM fSW VOOS VDD PSRR PSRRGSM ISY
Supply Current (Typically, 170 A Increase with ALC On)
Shutdown Current GAIN CONTROL Closed-Loop Gain Differential Input Impedance SHUTDOWN CONTROL Input Voltage High Input Voltage Low Wake-Up Time Shutdown Time Output Impedance
ISD Gain ZIN
SD = VDD SD = GND ISY 1 mA ISY 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND
VIH VIL tWU tSD ZOUT
Rev. A | Page 3 of 20
SSM2317
Parameter NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio
1
Symbol en SNR
Conditions VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded, gain = 18 dB, A-weighted PO = 1.4 W, RL = 8
Min
Typ 72 93
Max
Unit V dB
Although the SSM2317 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.
Rev. A | Page 4 of 20
SSM2317 ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at TA = 25C, unless otherwise noted. Table 2.
Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Continuous Output Power Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) ESD Susceptibility Rating 6V VDD VDD 3W -65C to +150C -40C to +85C -65C to +165C 300C 4 kV
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 9-Ball, 1.5 mm x 1.5 mm WLCSP PCB 1S0P 2S0P JA 162 76 JB 39 21 Unit C/W C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. A | Page 5 of 20
SSM2317 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1 CORNER
1 A 2 3
B
C
SSM2317
TOP VIEW (BALL SIDE DOWN) Not to Scale
07242-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1A 1B 1C 2A 2B 2C 3A 3B 3C Mnemonic IN- IN+ GND SD ALC_EN VDD VTH OUT- OUT+ Description Inverting Input. Noninverting Input. Ground. Shutdown Input. Active low digital input. Automatic Level Control Enable Input. Active high digital input. Power Supply. Variable Threshold. Inverting Output. Noninverting Output.
Rev. A | Page 6 of 20
SSM2317 TYPICAL PERFORMANCE CHARACTERISTICS
100 RL = 8 + 33H GAIN = 18dB 100 VDD = 3.6V 10 VDD = 2.5V 10 VDD = 5V GAIN = 18dB RL = 8 + 33H
THD + N (%)
THD + N (%)
1
1
0.1
VDD = 5V
0.1 1W 0.25W
0.01
0.01 0.5W
07242-003
0.001
0.01 0.1 OUTPUT POWER (W)
1
10
100
1k FREQUENCY (Hz)
10k
100k
Figure 3. THD + N vs. Output Power into 8 + 33 H, Gain = 18 dB
100
Figure 6. THD + N vs. Frequency, VDD = 5 V, RL = 8 + 33 H, Gain = 18 dB
100
RL = 4 + 33H GAIN = 18dB
VDD = 3.6V 10 VDD = 2.5V
THD + N (%)
10
VDD = 5V GAIN = 18dB RL = 4 + 33H
THD + N (%)
1
1
0.1
0.1
2W
0.01 VDD = 5V
0.01 1W 0.5W
07242-004
0.001
0.01 0.1 OUTPUT POWER (W)
1
10
100
1k FREQUENCY (Hz)
10k
100k
Figure 4. THD + N vs. Output Power into 4 + 33 H, Gain = 18 dB
100
Figure 7. THD + N vs. Frequency, VDD = 5 V, RL = 4 + 33 H, Gain = 18 dB
100
RL = 3 + 33H GAIN = 18dB
VDD = 3.6V 10 VDD = 2.5V
10
VDD = 5V GAIN = 18dB RL = 3 + 33H 3W
THD + N (%)
0.1
THD + N (%)
1
1
0.1 1.5W
0.01 VDD = 5V
07242-005
0.01 0.75W 100 1k FREQUENCY (Hz) 10k 100k
07242-008
0.001 0.0001
0.001
0.01 0.1 OUTPUT POWER (W)
1
10
0.001 10
Figure 5. THD + N vs. Output Power into 3 + 33 H, Gain = 18 dB
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 3 + 33 H, Gain = 18 dB
Rev. A | Page 7 of 20
07242-007
0.001 0.0001
0.001 10
07242-006
0.001 0.0001
0.001 10
SSM2317
100 VDD = 3.6V GAIN = 18dB RL = 8 + 33H
100
10
10
VDD = 2.5V GAIN = 18dB RL = 8 + 33H
THD + N (%)
THD + N (%)
1
1
0.1 0.125W 0.01 0.25W
07242-009
0.1
0.25W
0.5W
0.01 0.0625W
10k 100k
0.125W 1k FREQUENCY (Hz) 10k 100k
07242-012 07242-014 07242-013
0.001 10
100
1k FREQUENCY (Hz)
0.001 10
100
Figure 9. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 + 33 H, Gain = 18 dB
Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 + 33 H, Gain = 18 dB
100
10
VDD = 3.6V GAIN = 18dB RL = 4 + 33H
100
10
VDD = 2.5V GAIN = 18dB RL = 4 + 33H
THD + N (%)
1W 0.1 0.25W
THD + N (%)
1
1
0.5W
0.1
0.125W
0.01 0.5W 100 1k FREQUENCY (Hz) 10k 100k
07242-010
0.01 0.25W 0.001 10 100 1k FREQUENCY (Hz) 10k 100k
0.001 10
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 + 33 H, Gain = 18 dB
100
Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 + 33 H, Gain = 18 dB
100
10
VDD = 3.6V GAIN = 18dB RL = 3 + 33H
10 1.5W
VDD = 2.5V GAIN = 18dB RL = 3 + 33H
0.75W
THD + N (%)
0.1 0.75W 0.01 0.38W
07242-011
THD + N (%)
1
1
0.1
0.375W
0.01 0.188W 0.001 10
0.001 10
100
1k FREQUENCY (Hz)
10k
100k
100
1k FREQUENCY (Hz)
10k
100k
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 + 33 H, Gain = 18 dB
Figure 14. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 + 33 H, Gain = 18 dB
Rev. A | Page 8 of 20
SSM2317
4.4 4.2 4.0 RL = 8 + 33H
OUTPUT POWER (W)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
07242-015
07242-018 07242-020 07242-019
FREQUENCY = 1kHz GAIN = 18dB RL = 3 + 33H
DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER
SUPPLY CURRENT (mA)
3.8 RL = 4 + 33H 3.6 3.4 NO LOAD 3.2 3.0 2.8 2.6 2.5
10% 1%
3.0
3.5
4.0 4.5 5.0 SUPPLY VOLTAGE (V)
5.5
6.0
0 2.5
3.0
3.5 4.0 SUPPLY VOLTAGE (V)
4.5
5.0
Figure 15. Supply Current vs. Supply Voltage
Figure 18. Maximum Output Power vs. Supply Voltage, RL = 3 + 33 H, Gain = 18 dB
100 VDD = 2.5V RL = 8 + 33H VDD = 5V VDD = 3.6V
2.0 1.8 1.6 FREQUENCY = 1kHz GAIN = 18dB RL = 8 + 33H
90 80 70
OUTPUT POWER (W)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0
07242-016
EFFICIENCY (%)
60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 OUTPUT POWER (W) 1.2 1.4 1.6
10%
1%
0 2.5
Figure 16. Maximum Output Power vs. Supply Voltage, RL = 8 + 33 H, Gain = 18 dB
3.5
DO NOT EXCEED 3W CONTINUOUS OUTPUT POWER
Figure 19. Efficiency vs. Output Power into 8 + 33 H
100 90 80 70 VDD = 2.5V VDD = 3.6V VDD = 5V RL = 4 + 33H
3.0 2.5 2.0 10% 1.5 1% 1.0 0.5 0 2.5 FREQUENCY = 1kHz GAIN = 18dB RL = 4 + 33H
OUTPUT POWER (W)
EFFICIENCY (%)
4.5 5.0
07242-017
60 50 40 30 20 10
3.0
3.5 4.0 SUPPLY VOLTAGE (V)
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 OUTPUT POWER (W)
Figure 17. Maximum Output Power vs. Supply Voltage, RL = 4 + 33 H, Gain = 18 dB
Figure 20. Efficiency vs. Output Power into 4 + 33 H
Rev. A | Page 9 of 20
SSM2317
100 90 80 70 VDD = 2.5V VDD = 3.6V VDD = 5V POWER DISSIPATION (W) RL = 3 + 33H
0.5 0.6 RL = 3 + 33H VDD = 5V
EFFICIENCY (%)
0.4
60 50 40 30 20 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 OUTPUT POWER (W)
VDD = 3.6V
0.3 VDD = 2.5V
0.2
0.1
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 OUTPUT POWER (W)
Figure 21. Efficiency vs. Output Power into 3 + 33 H
Figure 24. Power Dissipation vs. Output Power into 3 + 33 H
0.12 RL = 8 + 33H 0.10
350 RL = 8 + 33H 300
SUPPLY CURRENT (mA)
VDD = 5V
POWER DISSIPATION (W)
0.08 VDD = 5V
250 200 150 100 50 VDD = 2.5V
VDD = 3.6V
0.06 VDD = 3.6V
0.04
0.02 VDD = 2.5V
07242-022
0
0.2
0.4
0.6 0.8 1.0 OUTPUT POWER (W)
1.2
1.4
1.6
0
0.2
0.4
0.6 0.8 1.0 OUTPUT POWER (W)
1.2
1.4
1.6
Figure 22. Power Dissipation vs. Output Power into 8 + 33 H
0.45 RL = 4 + 33H 0.40 VDD = 5V
Figure 25. Supply Current vs. Output Power into 8 + 33 H
800 RL = 4 + 33H 700 VDD = 5V 600 VDD = 3.6V 500 400 300 200 100
07242-023
07242-026
POWER DISSIPATION (W)
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 VDD = 2.5V VDD = 3.6V
SUPPLY CURRENT (mA)
VDD = 2.5V
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 OUTPUT POWER (W)
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 OUTPUT POWER (W)
Figure 23. Power Dissipation vs. Output Power into 4 + 33 H
Figure 26. Supply Current vs. Output Power into 4 + 33 H
Rev. A | Page 10 of 20
07242-025
0
0
07242-024
07242-021
0
0
SSM2317
1000 900 800 RL = 3 + 33H 4.2 VDD = 5V VDD = 3.6V 4.0 4.4
SUPPLY CURRENT (mA)
700 600 500 400 300 200 100 VDD = 2.5V
SUPPLY CURRENT (mA)
3.8 3.6 3.4 3.2 3.0 2.8
ALC = ON NO LOAD
ALC = OFF NO LOAD
07242-027
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 OUTPUT POWER (W)
3.0
3.5
4.0 4.5 5.0 SUPPLY VOLTAGE (V)
5.5
6.0
Figure 27. Supply Current vs. Output Power into 3 + 33 H
Figure 30. Supply Current vs. Supply Voltage, ALC Contribution
0 -10 -20 -30
100
90
80
VTH (%)
PSRR (dB)
-40 -50 -60 -70 -80 -90
07242-028
70
60
50
100
1k FREQUENCY (Hz)
10k
100k
1
10
100 RTH (k)
1k
10k
100k
Figure 28. Power Supply Rejection Ratio vs. Frequency
0 -10 -20
Figure 31. VTH vs. RTH
10
VDD = 5V RL = 8 + 33H ALC = ON VTH = 90% VTH = 70% VTH = 45%
1
OUTPUT POWER (W)
-30
CMRR (dB)
-40 -50 -60 -70 -80 -90
07242-029
0.1
0.01
100
1k FREQUENCY (Hz)
10k
100k
0.1 INPUT (V rms)
1
10
Figure 29. Common-Mode Rejection Ratio vs. Frequency
Figure 32. Input/Output Characteristic, VDD = 5 V, ALC = On
Rev. A | Page 11 of 20
07242-032
-100 10
0.001 0.01
07242-031
-100 10
40 0.1
07242-030
0
2.6 2.5
SSM2317
10 VDD = 3.6V RL = 8 + 33H ALC = ON VTH = 90% VTH = 70% 0.1 VTH = 45% HOLD TIME RELEASE TIME 1V/DIV VDD = 5V RL = 8 + 33H ALC = ON VTH = 70%
1
OUTPUT POWER (W)
INPUT
0.01
OUTPUT
07242-033
0.001 0.01
0.1 INPUT (V rms)
1
10
-100
0
100
200
300 400 500 TIME (ms)
600
700
800
900
Figure 33. Input/Output Characteristic, VDD = 3.6 V, ALC = On
Figure 36. Release Waveform
1V/DIV
6 5
1V/DIV
SD INPUT
INPUT
VOLTAGE (V)
4 3 OUTPUT 2 1 VDD = 5V RL = 8 + 33H ALC = ON VTH = 70%
07242-034
OUTPUT
0 -1 -4
07242-036
-0.2
0
0.2
0.4
0.6 0.8 1.0 TIME (ms)
1.2
1.4
1.6
1.8
0
4
8
12
16 20 TIME (ms)
24
28
32
36
Figure 34. Attack Waveform, 1 kHz Sine Wave
6
Figure 37. Turn-On Response
1V/DIV
SD INPUT 5
1V/DIV
INPUT ATTACK TIME
4
VOLTAGE (V)
VDD = 5V RL = 8 + 33H ALC = ON VTH = 70%
3 OUTPUT 2 1 0
OUTPUT
07242-035
-80
-40
0
40
80 120 TIME (s)
160
200
240
280
Figure 35. Attack Waveform, 3 kHz Sine Wave
Figure 38. Turn-Off Response
Rev. A | Page 12 of 20
07242-038
-0.1
0
0.1
0.2
0.3 0.4 0.5 TIME (ms)
0.6
0.7
0.8
0.9
-1 -120
07242-037
SSM2317 TYPICAL APPLICATION CIRCUITS
EXTERNAL GAIN SETTINGS = 80k/(10k + REXT ) 10F 0.1F 0.1F1 REXT 80k VBATT 2.5V TO 5.5V VDD
AUDIO IN+
IN+
10k
SSM2317
OUT+ MODULATOR (-) FET DRIVER OUT-
AUDIO IN-
0.1F1 R EXT
IN-
10k 80k
SHUTDOWN
SD
BIAS
ALC ALC_EN VTH RTH ALC ENABLE
INTERNAL OSCILLATOR
POP-AND-CLICK SUPPRESSION GND
1 INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 39. Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 80k/(10k + REXT )
10F 0.1F
VBATT 2.5V TO 5.5V VDD
AUDIO IN+
0.1F REXT
IN+
10k
80k
SSM2317
OUT+ MODULATOR (-) 0.1F R EXT IN- 10k 80k FET DRIVER OUT-
SHUTDOWN
SD
BIAS
ALC ALC_EN VTH RTH ALC ENABLE
INTERNAL OSCILLATOR
POP-AND-CLICK SUPPRESSION GND
07242-040
Figure 40. Single-Ended Input Configuration, User-Adjustable Gain
Rev. A | Page 13 of 20
07242-039
SSM2317 THEORY OF OPERATION
OVERVIEW
The SSM2317 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and, thus, reducing systems cost. The SSM2317 does not require an output filter but instead relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2317 uses a - modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. - modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. - modulation provides the benefits of reducing the amplitude of spectral components at high frequencies, that is, reducing EMI emission that might otherwise be radiated by speakers and long cable traces. Due to the inherent spread spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM2317 amplifiers. The SSM2317 also offers protection circuits for overcurrent and temperature protection. However, most of the time, output differential voltage is 0 V, due to the Analog Devices, Inc., patented three-level, - output modulation. This feature ensures that the current flowing through the inductive load is small. When the user wants to send an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 41 depicts three-level, - output modulation with and without input stimulus.
OUTPUT = 0V OUT+ OUT-
+5V 0V +5V 0V +5V 0V -5V
VOUT OUTPUT > 0V OUT+ OUT- VOUT OUTPUT < 0V OUT+ OUT- VOUT
+5V 0V +5V 0V +5V 0V +5V 0V +5V 0V 0V -5V
07242-041
GAIN
The SSM2317 has a default gain of 18 dB that can be reduced by using a pair of external resistors with a value calculated as follows: External Gain Settings = 80 k/(10 k + REXT)
Figure 41. Three-Level, - Output Modulation With and Without Input Stimulus
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of the audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, the following can be sources of audible transients: system power-up/power-down, mute/unmute, input source change, and sample rate change. The SSM2317 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation.
LAYOUT
As output power continues to increase, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layouts isolate critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emission and increase immunity to the RF field by a factor of 10 or more,
OUTPUT MODULATION DESCRIPTION
The SSM2317 uses three-level, - output modulation. Each output can swing from GND to VDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, there are always noise sources present. Due to this constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated.
Rev. A | Page 14 of 20
SSM2317
compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted with signal crossover. If the system has separate analog and digital ground and power planes, place the analog ground plane underneath the analog power plane, and, similarly, place the digital ground plane underneath the digital power plane. There should be no overlap between analog and digital ground planes or analog and digital power planes.
GAIN (dB)
24 21 18 15 12 9 6 3 0 -30 GAIN OUTPUT 12 9 6
0 -3 -6 -9
INPUT CAPACITOR SELECTION
The SSM2317 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD - 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If high-pass filtering is needed at the input, the input capacitor and the input resistor of the SSM2317 form a high-pass filter whose corner frequency is determined by the following equation: fC = 1/{2 x (10 k + REXT) x CIN} The input capacitor can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset of the amplifier and the dc PSRR performance.
-20
-10 INPUT (dBV)
0
10
Figure 42. Input/Output Characteristic and Gain
When the input level is small and below the ALC threshold value, the gain of the amplifier stays at 18 dB. When the input exceeds the ALC threshold value, the ALC begins to gradually reduce the gain from 18 dB to 3.5 dB.
OPERATING MODES
The ALC implemented on SSM2317 has two operating modes: compression and limiting. At the time the ALC is triggered for medium level input, the ALC is in compression mode. In this mode, an increase of the output signal is 1/3 of the increase of the input signal. For example, if the input signal increases by 3 dB, the ALC reduces the amplifier gain by 2 dB and thus the output signal only increases by 1 dB. As the input signal becomes very large, the ALC transitions into limiting operation mode. In this mode, the output stays at a given threshold level, VTH, even if the input signal grows larger. For example, when a large input signal increases by 3 dB, the ALC reduces the amplifier gain by 3 dB and thus the output increases 0 dB. When the amplifier gain is reduced to 3.5 dB, ALC cannot further reduce the gain and the output increases again. To avoid potential speaker damage, the maximum input signal should not be large enough to exceed the maximum attenuation (3.5 dB) of the limiting operational mode.
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality low ESL, low ESR capacitor, usually of around 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 F capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2317 helps maintain efficient performance.
ATTACK TIME, HOLD TIME, AND RELEASE TIME
When the amplifier input exceeds a preset threshold, ALC reduces amplifier gain rapidly until its output settles to a target level. This gain level is maintained for a certain period. If the input does not exceed the threshold again, ALC increases the gain gradually. The attack time is the time taken to reduce the gain from maximum to minimum. The hold time is the time to sustain the reduced gain. The release time is the time taken to increase the gain from minimum to maximum. These times are shown in Table 5. Table 5. Attack, Hold, and Release Times
Time Attack Time Hold Time Release Time Duration (ms) 0.1 35 550
AUTOMATIC LEVEL CONTROL (ALC)
Automatic level control (ALC) is a function that automatically adjusts amplifier gain to generate desired output amplitude with reference to a particular input stimulus. The primary motivation for the use of ALC is to protect an audio power amplifier or speaker load from the damaging effects of clipping or current overloading. This is accomplished by limiting the amplifier's output amplitude upon reaching a preset threshold voltage. A less intuitive benefit of ALC is that it makes sound sources with a wide dynamic range more intelligible by boosting low level signals yet limits very high level signals. Figure 42 shows input vs. output and gain characteristics of ALC that is implemented in the SSM2317.
Rev. A | Page 15 of 20
07242-042
-12
OUTPUT (dBV)
3
SSM2317
OUTPUT THRESHOLD
The maximum output amplitude threshold (VTH) during the limiting mode can be changed from 90% to 45% of VDD by having an external resistor, RTH, between the VTH pin and GND. Shorting the VTH pin to GND sets VTH to 90% of VDD. Leaving the VTH pin unconnected sets VTH to 45% of VDD. The relation of RTH to VTH is shown by the following equation:
VTH = 0.9 x 50 k + RTH 50 k + 2 x RTH x VDD
1400 1200 1000 4.2V (8) 800 3.6V (8) 600 400 200 0 0.1 5V (8)
OUTPUT POWER (mW)
Maximum output power is derived from VTH by the following equation:
2.5V (8)
POUT
VTH 2 = RSP
2
1
10 RTH (k)
100
1k
10k
Figure 44. Maximum Output Power vs. RTH
where RSP is the speaker impedance. Figure 43 shows the relationship between the RTH value and VTH. Figure 44 shows the relationship between the maximum output power and the RTH value.
100
ENABLE/DISABLING ALC
The ALC function is enabled when the ALC_EN pin is set to VDD. The ACL function can be enabled and disabled during amplifier operation. As a result of enabling ALC, ISY increases by 100 A and there is less than 50 A source current from the VTH pin to GND via RTH. When ALC is disabled, the source current is 0 A and the VTH pin is tied to GND.
90
OUTPUT SWING (% of VDD)
80
70
60
50
1
10 RTH (k)
100
1k
10k
Figure 43. Output Threshold (VTH) vs. RTH
07242-043
40 0.1
Rev. A | Page 16 of 20
07242-044
SSM2317 OUTLINE DIMENSIONS
A1 BALL CORNER 1.490 1.460 SQ 1.430 0.655 0.600 0.545 SEATING PLANE 0.350 0.320 0.290
3 2 1 A
B
0.50 BALL PITCH TOP VIEW
(BALL SIDE DOWN)
C
0.385 0.360 0.335
BOTTOM VIEW 0.270 0.240 0.210
(BALL SIDE UP)
Figure 45. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-2) Dimensions shown in millimeters
ORDERING GUIDE
Model SSM2317CBZ-REEL 1 SSM2317CBZ-REEL71 SSM2317-EVALZ1 SSM2317-MINI-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Evaluation Board
Package Option CB-9-2 CB-9-2
101507-C
Branding Y0Z Y0Z
Z = RoHS Compliant Part.
Rev. A | Page 17 of 20
SSM2317 NOTES
Rev. A | Page 18 of 20
SSM2317 NOTES
Rev. A | Page 19 of 20
SSM2317 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07242-0-6/08(A)
Rev. A | Page 20 of 20

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